Review Article
A Model-Driven Approach for Hybrid Power Estimation in Embedded Systems Design
Chiraz Trabelsi,1 Rabie Ben Atitallah,2 Samy Meftali,1 Jean-Luc Dekeyser,1 and Abderrazek Jemai3,41INRIA Lille Nord Europe-LIFL-USTL-CNRS, 40 Avenue Halley, 59650 Villeneuve d’Ascq, France
2LAMIH, University of Valenciennes, Le Mont Houy, 59313 Valenciennes, France
3LIP2 Laboratory, Faculty of Science of Tunis, 2092 Manar 2 Tunis, Tunisia
4Institut National des Sciences Appliquées et de Technologie (INSAT), B.P. 676, 1080 Tunis Cedex, Tunisia
Received 15 December 2010; Accepted 21 February 2011
Academic Editor: Tulika Mitra
Copyright © 2011 Chiraz Trabelsi et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.
Abstract
As technology scales for increased circuit density
and performance, the management of power consumption in
system-on-chip (SoC) is becoming critical. Today, having the
appropriate electronic system level (ESL) tools for power
estimation in the design flow is mandatory. The main challenge
for the design of such dedicated tools is to achieve a better
tradeoff between accuracy and speed. This paper presents a
consumption estimation approach allowing taking the consumption
criterion into account early in the design flow during the
system cosimulation. The originality of this approach is that
it allows the power estimation for both white-box intellectual
properties (IPs) using annotated power models and black-box
IPs using standalone power estimators. In order to obtain
accurate power estimates, our simulations were performed at the
cycle-accurate bit-accurate (CABA) level, using SystemC. To
make our approach fast and not tedious for users, the simulated
architectures, including standalone power estimators, were generated
automatically using a model driven engineering (MDE)
approach. Both annotated power models and standalone power
estimators can be used together to estimate the consumption of
the same architecture, which makes them complementary. The
simulation results showed that the power estimates given by both
estimation techniques for a hardware component are very close,
with a difference that does not exceed 0.3%. This proves that,
even when the IP code is not accessible or not modifiable, our
approach allows obtaining quite accurate power estimates
that early in the design flow thanks to the automation offered
by the MDE approach.
1. Introduction
While the increasing integration of systems-on-chip (SoC) permits to increase their computation performances, the underlying power dissipation has become a dominant concern. Therefore, power consumption becomes a major criterion to take into account during design space exploration. An important design challenge is to find a tradeoff between performance and power consumption early in the design flow in order to satisfy time-to-market constraints. Cracking the power problem while maintaining acceptable design productivity requires estimation methods that support abstraction and automation.
Low-level energy estimation methods take into account many details of the simulated SoC, which leads to very slow simulations that increase the design time significantly, especially for complex systems. Despite the accuracy of such methods, their slowness represents an obstacle to productivity. Therefore, more abstract estimation techniques are required. The cycle-accurate bit-accurate (CABA) level [1] is an abstraction level for a system description that is higher than the register transfer level (RTL). It allows obtaining faster simulations than those performed using RTL. Usually, to move from the RTL to the CABA level, hardware implementation details are hidden from the processing part of the system while preserving system behavior at the clock cycle level. The bit-accurate implies that a communication protocol is used between components at the bit level. At the CABA level, the behavior of the system can be simulated cycle by cycle, which permits obtaining quite accurate power estimates. Thus, this abstraction level allows for a tradeoff between simulation speed and accuracy. Therefore, we chose this abstraction level for our simulations. Due to the tremendous amount of hardware resources available in SoCs, design tools and methodologies are required to decrease the design complexity. Implementing these systems directly at a low level such as RTL can lead to errors. Therefore, an efficient design methodology, such as model driven engineering (MDE) [2], is needed in order to make the SoC design easy and not tedious, by making the low-level technical details transparent to designers. In MDE, models become a means of productivity. The graphical nature of MDE offered by the unified modeling language (UML) makes the comprehensibility of a system easier and allows users to model their systems at a high abstraction level, reuse, modify, and extend their models. Using the automation offered by MDE, the whole code necessary for the simulation of an SoC can be generated automatically from models describing the system. In order to use the MDE for a high-level description of a system in a specific domain such as embedded systems, UML profiles are used. A UML profile is a set of stereotypes that add specific information to a UML model in order to describe a system related to a specific domain. Several UML profiles target embedded systems design such as the modeling and analysis of real-time and embedded systems (MARTE) [3] profile. MARTE is a standard profile promoted by the object management group (OMG). Gaspard2 [4] is a SoC codesign framework that is based on MDE to describe both the architecture and application parts of a system at a high abstraction level. Gaspard2 uses the MARTE profile for embedded systems modeling. It targets many technologies such as VHDL and SystemC using model transformations. The generated SystemC code for a modeled system using Gaspard2 is used for co-simulation in order to determine the system performance in terms of execution time. But, until now, the energy estimation has not been fully integrated into Gaspard2. Our contribution in this framework is to integrate power estimation at the modeling level of Gaspard2 as well as at the simulation level, allowing of automation the energy estimation in the Gaspard2 design flow. An accurate power estimation method is based on a characterization phase using low-level tools in order to determine the consumption of the different activities of a hardware component accurately. The obtained power model is then used during simulations to estimate the consumption of the related component. During simulation, the simulator detects whether an activity has occurred for a given component and adds its consumption cost to the total consumption of the component. The most important challenge here is how to detect these activities especially if the intellectual property (IP) description codes are not accessible. The main contribution of this paper is to present a hybrid energy estimation approach for SoC, in which the consumption of both white-box IPs and black-box IPs can be estimated. Based on model-driven engineering, this approach allows to take the consumption criterion into account early in the design flow, during the co-simulation of SoC. In a previous work [5], we presented an annotated power model estimation technique for white-box IPs where counters are introduced into the code of the IPs. A counter is incremented whenever its related activity occurs. This technique was used in this present work, along with the standalone power estimator technique used for black-box IPs. The standalone power estimation modules were generated using MDE and connected between the components in order to detect their activities through the signals that they exchange. To test this approach, systems containing white-box IPs and black-box IPs and their related estimation modules were modeled in the Gaspard2 framework. Using the MDE model transformations, the code required for simulation can be generated automatically. Finally, consumption estimates can be obtained during simulations. The rest of this paper is organized as follows. Section 2 gives a summary of the related works. An overview of MDE and the Gaspard2 framework is provided in Section 3. Section 4 illustrates our hybrid approach for energy estimation. Section 5 describes the MDE approach used to implement our estimation modules and their integration in the Gaspard2 framework. This paper ends with simulation results in Section 6.
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